The present invention relates to devices used in the testing and inking of dies fabricated on a semiconductor wafer substrate. More particularly, the present invention relates to an inking apparatus which has multi-positioning and adjusting capability in the inking of multiple, disparately-located defective dies on a semiconductor wafer substrate.
A conventional method used by the semiconductor industry in the manufacturing of semiconductor integrated circuits includes the steps of fabrication, wafer sort, assembly and test, respectively. In the fabrication step, as many as several thousand dies (integrated circuits) are formed onto a semiconductor wafer. In the wafer sort step, each of the dies on the wafer is tested to determine its electrical characteristics and operability, and defective dies are distinguished from operable dies. The defective dies are often marked by an ink mark at the wafer sorting step. In the assembly step, the unmarked, operable dies are assembled into a package, and in the test step, the packaged integrated circuits are tested for operability and reliability.
At the wafer sort step, the dies are tested to establish which dies on the wafer function properly. Each die is tested to all functional product specifications for both DC and AC parameters. Four testing objectives are pursued: (1) chip functionality, in which all chip functions are tested to ensure that only fully-functional chips are assembled and packaged in subsequent steps; (2) chip sorting, in which chips are separated or sorted on the basis of their operating speed performance under various voltage and timing conditions; (3) fab yield response, which yields important information that may lead to improvements in the overall fabrication process; and (4) test coverage, in which high test coverage of the internal device nodes is achieved at the lowest possible cost. The wafer sort procedure is similar to the in-line parametric test except that every die on the wafer is tested, in many cases using the same automated test equipment (ATE). Furthermore, the wafer sort procedure is usually located in a separate facility under less stringent purity conditions than those in which the parametric test is carried out, since wafer fabrication is essentially complete.
In automated wafer handling during wafer sort, a correlation wafer is used to verify tester setup. The correlation wafer is a control wafer the functionality of which has been verified and ensures that the testing system is working properly. After indexing from the cassette to the prober, the wafers are mounted on a vacuum chuck with Z (vertical) positioning. Using software, mechanical probe needles are aligned and contacted with bond pads on the wafer to establish electrical communication between the testing equipment and the dies on the wafer. The probes are interfaced with the ATE to perform the range of AC functional tests based on test algorithms. The type, number and order of tests are defined by the test program.
After testing, die found to be defective are labeled in a computer database to exclude the die from subsequent packaging steps. The labeling method is typically performed by placing a drop of ink on each unacceptable die. Because the ink marking process can be messy and introduce possible contaminants onto the chip, electronic wafer maps are increasingly being used to create a computer image of chip location and test results to categorize good and bad die on the wafer. At the chip assembly stations, the electronic wafer maps are downloaded into an equipment database to ensure that defective chips will not be packaged.
Typically, the die on a wafer are inked by operation of an inking head the position of which over the wafer is automatically controlled using a software-actuated controller. In the inking of multiple dies at separate locations on the wafer, the ink head must be moved between multiple positions on the wafer by operation of the software-controlled controller. However, this procedure is time-consuming and inefficient. An apparatus is therefore needed which facilitates manual multi-positioning capability of the ink head over the wafer for inking multiple, disparately-spaced die on the wafer.
An object of the present invention is to provide an inking apparatus which has multi-positioning capability in the inking of defective dies on a semiconductor wafer.
Another object of the present invention is to provide an inking apparatus which may be manually-operated.
Still another object of the present invention is to provide an inking apparatus which reduces the amount of time required for inking multiple dies on a semiconductor wafer.
Yet another object of the present invention is to provide an apparatus which facilitates quick and yet accurate adjustment of an inking probe in the inking of defective dies on a semiconductor wafer.
A still further object of the present invention is to provide an apparatus having an inking head which can be adjusted in the X, Y and Z directions as needed in inking multiple, disparately-located, defective dies on a semiconductor wafer.
In accordance with these and other objects and advantages, the present invention comprises an inking apparatus including an inking head which is manually adjustable in the X, Y and Z directions to facilitate quick and easy positioning of an inking probe in proximity to a defective die on a semiconductor wafer to ink and mark the die for exclusion from further processing. A horizontal positioning plate is horizontally adjustably mounted on a base plate, and an angular adjustment arm is angularly adjustably mounted on the horizontal positioning plate. The inking head is vertically adjustably mounted on the end of the angular adjustment arm and carries an ink reservoir from which ink is dispensed through an inking probe to the dies on the wafer.